Self-aligned double patterning (SADP) techniques, are currently used in back-end-of-the-line (BOEL) construction of ultra-high density integrated circuits to provide an electrical interconnection system which includes multiple arrays of parallel metal lines disposed in several levels of dielectric layers. The dielectric layers are typically interconnected through a system of metalized vias. Conventionally, within an array of metal lines, the direction longitudinal to the metal lines is designated the “Y” direction and the direction perpendicular, or lateral, to the metal lines is designated the “X” direction.
Such SADP techniques typically involve the use of a lithographic mask (designated herein as a “mandrel mask”) to pattern and print an array of longitudinally extending parallel mandrels onto a top surface of a hardmask layer. Pairs of self-aligned spacers are then formed on both sidewalls of each mandrel.
Each combination of mandrel and associated spacer pair is separated by exposed parallel portions of the hardmask layer, which are absent any overlaying mandrels or spacers. The mandrels are patterned down into a dielectric layer of the integrated circuit to form mandrel metal lines. The exposed portions of the hardmask layer are also patterned down into the dielectric layer to form non-mandrel metal lines. Therefore, each array of parallel metal lines in an interconnection system formed using an SADP process will include alternating mandrel and non-mandrel metal lines, which are separated by a distance equal to the width of the self-aligned spacers.
In order to provide functionality between devices, such as transistors, capacitors and the like, in the integrated circuit, a plurality of cuts must be lithographically patterned into the mandrel and non-mandrel metal lines of an array at specific locations to direct current flow between the dielectric layers and the devices. Generally, another lithographic mask (designated herein as a “mandrel line cut mask” or “first cut mask”) is used to pattern such mandrel cuts into the mandrel metal lines. Also generally yet another lithographic mask (designated herein as a “non-mandrel line cut mask” or “second cut mask”) is used to pattern such non-mandrel cuts into the non-mandrel metal lines.
Accordingly, a typical SADP process for patterning arrays of metal lines in a complex interconnection system for an integrated circuit requires at least three masks: a mandrel mask, a mandrel line cut mask, and a non-mandrel line cut mask. Development and use of such masks requires complex, state of the art technology, especially when lithographically printing aggressively small features in such technology class sizes as the 14 nanometer (nm) class and beyond. Therefore it is desirable to keep the number of masks to a minimum due to the large costs associated with the development and use of such masks.
However, there is often a requirement for relatively large planar transition regions between functioning logic blocks where there can be no devices or lines at all. These transition regions are commonly called “ANA regions” (also known as “white regions” or “buffer regions”) and are typically between 50 to 100 nanometers (nm) wide and several hundred nm long or more. The ANA regions typically extend longitudinally in the Y direction (parallel to the arrays of metal lines in the plan of the ANA region) or longitudinally in the X direction (perpendicular to the arrays of metal lines in the plan of the ANA region). However, the ANA regions can extend in several different directions and may have complex shapes.
ANA regions are used to provide required separation between different logic blocks, such as a Central Processing Unit (CPU) block, a Static Random Access Memory (SRAM) block or the like, that are designed by different diverse teams during the manufacturing process of a complex integrated circuit. The ANA regions may be required to: prevent electromagnetic interference between blocks, eliminate induced currents between blocks, prevent heat transfer between blocks, provide a buffer space for safety reasons between blocks or the like.
Unfortunately, conventional methods of manufacturing currently require at least one additional ANA mask, and sometimes several different ANA masks, to form the ANA regions on an integrated circuit. These ANA masks are in addition to the mandrel mask, first cut mask and second cut mask utilized in SADP techniques for the formation of metal lines in an interconnection system of an integrated circuit. Each additional ANA mask adds significant cost and labor to the design of the integrated circuit.
Accordingly, there is a need for a method of forming ANA regions on an integrated circuit with a minimum of ANA masks. Additionally, there is a need to eliminate the use of a mask dedicated to just the formation of ANA regions in an integrated circuit. Moreover, there is a need for a method of combining the formation of ANA regions with the formation of metal line cuts utilizing only a first cut mask and a second cut mask.